元器件:ic:memory:ddr:start
差别
这里会显示出您选择的修订版和当前版本之间的差别。
| 两侧同时换到之前的修订记录前一修订版后一修订版 | 前一修订版 | ||
| 元器件:ic:memory:ddr:start [2026/01/16 08:34] – [常用标准] hwwiki | 元器件:ic:memory:ddr:start [2026/06/15 06:57] (当前版本) – [表] hwwiki | ||
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| DDR(Double Data Rate SDRAM )常用于电脑等标准设备。各版本差异如下: | DDR(Double Data Rate SDRAM )常用于电脑等标准设备。各版本差异如下: | ||
| - | | **Name** | + | | **Name** |
| - | | **Gen** | + | | **Gen** |
| - | |::: | + | | ::: | ::: |
| - | | **DDR** | + | | **DDR** |
| - | |:::| **DDR-266** | + | | ::: | **DDR-266** |
| - | |:::| **DDR-333** | + | | ::: | **DDR-333** |
| - | |:::| **DDR-400** | + | | ::: | **DDR-400** |
| - | | **DDR2** | + | | **DDR2** |
| - | |:::| **DDR2-533** | + | | ::: | **DDR2-533** |
| - | |:::| **DDR2-667** | + | | ::: | **DDR2-667** |
| - | |:::| **DDR2-800** | + | | ::: | **DDR2-800** |
| - | | **DDR3** | + | | **DDR3** |
| - | |:::| **DDR3-1066** | + | | ::: | **DDR3-1066** |
| - | |:::| **DDR3-1333** | + | | ::: | **DDR3-1333** |
| - | |:::| **DDR3-1600** | + | | ::: | **DDR3-1600** |
| - | |:::| **DDR3-1866** | + | | ::: | **DDR3-1866** |
| - | |:::| **DDR3-2133** | + | | ::: | **DDR3-2133** |
| - | | **DDR4** | + | | **DDR4** |
| - | |:::| **DDR4-1866** | + | | ::: | **DDR4-1866** |
| - | |:::| **DDR4-2133** | + | | ::: | **DDR4-2133** |
| - | |:::| **DDR4-2400** | + | | ::: | **DDR4-2400** |
| - | |:::| **DDR4-2666** | + | | ::: | **DDR4-2666** |
| - | |:::| **DDR4-2933** | + | | ::: | **DDR4-2933** |
| - | |:::| **DDR4-3200** | + | | ::: | **DDR4-3200** |
| - | | **DDR5** | + | | **DDR5** |
| - | |:::| **DDR5-3600** | + | | ::: | **DDR5-3600** |
| - | |:::| **DDR5-4000** | + | | ::: | **DDR5-4000** |
| - | |:::| **DDR5-4400** | + | | ::: | **DDR5-4400** |
| - | |:::| **DDR5-4800** | + | | ::: | **DDR5-4800** |
| - | |:::| **DDR5-5200** | + | | ::: | **DDR5-5200** |
| - | |:::| **DDR5-5600** | + | | ::: | **DDR5-5600** |
| - | |:::| **DDR5-6000** | + | | ::: | **DDR5-6000** |
| - | |:::| **DDR5-6400** | + | | ::: | **DDR5-6400** |
| - | |:::| **DDR5-6800** | + | | ::: | **DDR5-6800** |
| - | |:::| **DDR5-7200** | + | | ::: | **DDR5-7200** |
| - | |:::| **DDR5-7600** | + | | ::: | **DDR5-7600** |
| - | |:::| **DDR5-8000** | + | | ::: | **DDR5-8000** |
| - | |:::| **DDR5-8400** | + | | ::: | **DDR5-8400** |
| 行 98: | 行 98: | ||
| |:::| **LPDDR5X-7500** | |:::| **LPDDR5X-7500** | ||
| |:::| **LPDDR5X-8533** | |:::| **LPDDR5X-8533** | ||
| + | |||
| + | ===== 术语 ===== | ||
| + | |||
| + | ==== Prefetch(预取) ==== | ||
| + | |||
| + | 由于DDR内部存储单元,其电容充放电物理条件的限制,频率无法持续提升,长期保持在100M~300MHz左右,DDR1~5速率的提升主要依赖于Prefetch,如下图所示[([[https:// | ||
| + | |||
| + | {{: | ||
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| + | Prefetch类似于串并转换,把并行的多个慢数据,转换成高速的串行数据,如下图所示: | ||
| + | |||
| + | {{: | ||
| + | |||
| + | {{: | ||
| + | |||
| + | 硬件上具体的实现,以2n为例如下图所示[({{ : | ||
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| + | {{: | ||
| + | |||
| + | {{: | ||
| + | |||
| + | 因Prefetch,chip cell和Bus之间的关系如下表(以Bus Width x4为例)[([[https:// | ||
| + | |||
| + | | DDRx | Cell || Pre-fetch\\ =N | Bus ||| | ||
| + | |:::| cell阵列接口位宽 | ||
| + | | DDR1 | X8 | 200Mhz | ||
| + | | DDR2 | X16 | 200Mhz | ||
| + | | DDR3 | X32 | 200Mhz | ||
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元器件/ic/memory/ddr/start.1768523656.txt.gz · 最后更改: 2026/01/16 08:34 由 hwwiki