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元器件:ic:memory:ddr:start

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目录

DDR(Double Date Rate)

标准组织为JEDEC，官网jedec.org，早期的标准文档个人注册后可免费下载，近期发布的需要付费

常用标准

DDR:

LPDDR:

版本差异

DDR(Double Data Rate SDRAM )常用于电脑等标准设备。各版本差异如下：

Name Chip Bus Banks Density VDD VDDQ Difference References
Gen Standard Clock rate Pre-fetch Clock rate Transfer rate CL-tRCD-tRP tCK min Width
(MHz) (MHz) (MT/s) (tCK) ns (V) (V)
DDR DDR-200 100 2n 100 200 - 10 x4/x8/x16 4 64Mb~1Gb 2.5 2.5/3.3 Gen. 1 DDR1 JESD79F：
Address Assignment Table 1a TSOP2 Package
Address Assignment Table 1b BGA Package
Table 11 – AC Electrical Characteristics (Timing Table)
DDR-266 133 133 266 - 7.5
DDR-333 166+2⁄3 166+2⁄3 333 - 6
DDR-400 200 200 400 2.5–3–3
3–3–3
3–4–4 		5 2.6 2.6
DDR2 DDR2-400 100 4n 200 400 3-3-3
4-4-4 		5 x4/x8/x16 4/8 128Mb~4Gb 1.8 ODT(on-die termination)
Post CAS
OCD（Off-Chip Driver） 		DDR2 JESD79-2F:
2.4 DDR2 SDRAM addressing
6 AC & DC operating conditions
DDR2-533 133+1⁄3 266+2⁄3 533+1⁄3 3-3-3
4-4-4 		3.75
DDR2-667 166+2⁄3 333+1⁄3 666+2⁄3 4-4-4
5-5-5 		3
DDR2-800 200 400 800 4-4-4
5-5-5
6-6-6 		2.5
DDR3 DDR3-800 100 8n 400 800 5-5-5
6-6-6 		2.5 x4/x8/x16 8 512Mb~8Gb DDR3: 1.5
DD3L: 1.35
DDRU: 1.25 		Dynamic ODT
ZQ
Reset
Point-to-Point 		DDR3 JESD79-3F：
2.11 DDR3 SDRAM Addressing
7.1 Recommended DC Operating Conditions
12.3 Standard Speed Bins

DDR3L JESD79-3-1A-01:
Table 2 — Recommended DC Operating Conditions - DDR3L (1.35 V) operation

DDR3U JESD79-3-2:
Table 1 — Recommended DC Operating Conditions - DDR3U (1.25 V) operation
DDR3-1066 133+1⁄3 533+1⁄3 1066+2⁄3 6-6-6
7-7-7
8-8-8 		1.875
DDR3-1333 166+2⁄3 666+2⁄3 1333+1⁄3 7-7-7
8-8-8
9-9-9
10-10-10 		1.5
DDR3-1600 200 800 1600 8-8-8
9-9-9
10-10-10
11-11-11 		1.25
DDR3-1866 233+1⁄3 933+1⁄3 1866+2⁄3 10-10-10
11-11-11
12-12-12
13-13-13 		1.07
DDR3-2133 266+2⁄3 1066+2⁄3 2133+1⁄3 11-11-11
12-12-12
13-13-13
14-14-14 		0.938
DDR4 DDR4-1600 200 8n 800 1600 10-10-10
11-11-11
12-12-12 		1.25 x4/x8/x16 4Bank x 2/4BG 2Gb~16Gb 1.2

VPP: 2.5
( DRAM Activating ) 		Data Bus Inversion (DBI)
Bank Group
POD
CRC for Data Bus 		DDR4 JESD79-4C:
2.8 DDR4 SDRAM Addressing
7 AC & DC Operating Conditions
10 Speed Bin
DDR4-1866 233+1⁄3 933+1⁄3 1866+2⁄3 12-12-12
13-13-13
14-14-14 		1.071
DDR4-2133 266+2⁄3 1066+2⁄3 2133+1⁄3 14-14-14
15-15-15
16-16-16 		0.937
DDR4-2400 300 1200 2400 15-15-15
16-16-16
17-17-17
18-18-18 		0.833
DDR4-2666 333+1⁄3 1333+1⁄3 2666+2⁄3 17-17-17
18-18-18
19-19-19
20-20-20 		0.75
DDR4-2933 366+2⁄3 1466+2⁄3 2933+1⁄3 19-19-19
20-20-20
21-21-21
22-22-22 		0.682
DDR4-3200 400 1600 3200 20-20-20
22-22-22
24-24-24 		0.625
DDR5 DDR5-3200 200 16n 1600 3200 22-22-22
26-26-26
28-28-28 		0.625 x4/x8/x16 Min8:
2Bank x 4BG

Max32:
4Bank x8BG 		8Gb~64Gb 1.1

VPP: 1.8
( DRAM Activating ) 		On-die ECC DDR5 JESD79-5:
2.7 DDR5 SDRAM Addressing
6.2 Recommended DC Operating Conditions 10 Speed Bins
DDR5-3600 225 1800 3600 26-26-26
30-30-30
32-32-32 		0.555
DDR5-4000 250 2000 4000 28-28-28
32-32-32
36-36-36 		0.5
DDR5-4400 275 2200 4400 32-32-32
36-36-36
40-40-40 		0.454
DDR5-4800 300 2400 4800 34-34-34
40-40-40
42-42-42 		0.416
DDR5-5200 325 2600 5200 38-38-38
42-42-42
46-46-46 		0.384
DDR5-5600 350 2800 5600 40-40-40
46-46-46
50-50-50 		0.357
DDR5-6000 375 3000 6000 42-42-42
50-50-50
54-54-54 		0.333
DDR5-6400 400 3200 6400 46-46-46
52-52-52
56-56-56 		0.312
DDR5-6800 425 3400 6800 TBD
DDR5-7200 450 3600 7200
DDR5-7600 475 3800 7600
DDR5-8000 500 4000 8000
DDR5-8400 525 4200 8400

LPDDR(Low Power Double Data Rate SDRAM)常用于手机等有低功耗要求的设备。各版本差异如下：

Name Chip Bus Banks Density Voltage Difference
https://en.wikipedia.org/wiki/LPDDR 		References
Gen Standard Pre-fetch Clock rate Transfer rate tCK min Width
(MHz) (MT/s) ns
LPDDR LPDDR200 2n 100 200 10 x16/x32 4 64Mb~2Gb VDD: 1.8V
VDDQ: 1.8V 		VS DDR：
VDD/VDDQ is reduced from 2.5 to 1.8 V
Temperature-compensated refresh
Partial array self refresh,
“Deep power down” mode
Smaller Package 		LPDDR JESD209B:
Table 2 — LPDDR SDRAM Addressing Table
7 AC & DC Operating Conditions
LPDDR266 133 266 7.5
LPDDR333 166+2⁄3 333 6
LPDDR370 185 370 5.4
LPDDR400 200 400 5
LPDDR2 LPDDR2-333 S2: 2n
S4: 4n 		166 333 6 x8/x16/x32 4/8 64Mb~8Gb VDD1: 1.8V
VDDCA: 1.2V
VDDQ: 1.2V
VDD2:
S2A-N/A,
S2B/4B-1.2V,
S4A-1.35V 		some additional partial array refresh options LPDDR2 JESD209-2F:
Table 3 — LPDDR2 SDRAM Addressing
7 AC & DC Operating Conditions
Table 103 — LPDDR2 AC Timing Table
LPDDR2-400 200 400 5
LPDDR2-533 266 533 3.75
LPDDR2-667 333 667 3
LPDDR2-800 400 800 2.5
LPDDR2-933 466 933 2.15
LPDDR2-1066 533 1066 1.875
LPDDR3 LPDDR3-333 8n 166 333 6 x16/x32 8 1Gb~16Gb
(32Gb TBD) 		VDD1: 1.8V
VDDCA: 1.2V
VDDQ: 1.2V
VDD2: 1.2V 		Write-leveling and command/address training
Optional on-die termination (ODT),
Low-I/O capacitance
Package-on-package (PoP) and discrete packaging- 		LPDDR3 JESD209-3C:
Table 3 — LPDDR3 SDRAM Addressing
6 AC & DC Operating Conditions
11.4 LPDDR3 Read and Write Latencies
LPDDR3-400 400 800 2.5
LPDDR3-533 533 1066 1.875
LPDDR3-667 600 1200 1.67
LPDDR3-800 667 1333 1.5
LPDDR3-933 733 1466 1.36
LPDDR3-1066 800 1600 1.25
LPDDR4/4X LPDDR4-1600 16n 800 1600 1.25 x8/x16 8/Channel 1Gb~16Gb
(Single Channel)
2Gb~32Gb
(Dual Channel) 		VDD1: 1.8V
VDDQ:
1.1V (LPDDR4)
0.6V (LPDDR4X)
VDD2: 1.1V 		Change I/O standard to low-voltage swing-terminated logic (LVSTL)
Change from a 10-bit DDR command/address bus to a 6-bit SDR bus
Change from one 32-bit wide bus to two independent 16-bit wide buses
Self-refresh is enabled by dedicated commands- 		LPDDR4 JESD209-4D:
3.1 LPDDR4 SDRAM Addressing
6 AC & DC Operating Conditions
Table 218 — Clock AC Timings

LPDDR4X JESD209-4-1:
Table 13 — Recommended DC Operating Conditions
LPDDR4-2400 1200 2400 0.833
LPDDR4-3200 1600 3200 0.625
LPDDR4-4266 2133 4266 0.468
LPDDR5/5X LPDDR5-5500 16n/32n 2750 5500 1.453 x8/x16 4Banks/4Bank Group
or 8Banks
or 16Banks 		2Gb~32Gb VDD1: 1.8V
VDDQ: 0.5V (SPEC Range-1)
or 0.3V (SPEC Range-2)
or 0.27~0.57V (Allowable Range)
VDD2H: 1.05V
VDD2L: 1.05V (Single Core) 0.9V (Dual Core) 		Max 4 bank groups
Data-Copy and Write-X (all one or all zero) commands to decrease data transfer
Dynamic frequency and voltage scaling
A new clocking architecture, where commands use a quarter-speed master clock (CK)
One set of full-speed clocks per byte (vs. per 16 bits in LPDDR4)
Elimination of the Clock Enable (CKE) pin 		LPDDR5 JESD209-5B:
2.2.4 LPDDR5 SDRAM Addressing
Table 396 — Recommended Voltage operating conditions
2.2.5 Speed Grade
LPDDR5-6400 3200 6400 1.25
LPDDR5X-7500 3750 7500 1.0667
LPDDR5X-8533 4266.5 8533 0.9376

参数

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元器件/ic/memory/ddr/start.1769914448.txt.gz · 最后更改: 2026/02/01 10:54 由 hwwiki